This invention relates generally to computer system architectures and more particularly to an integrated computing system.
FIG. 4 illustrates a schematic block diagram of a known computing system. As shown, the computing system includes components within a chassis, i.e., the hardware box, and external devices. As shown, the external devices include speakers, a monitor, external peripheral devices such as printers, memory backups, etc. Within the chassis, the computer system includes a motherboard, memory, internal peripheral devices, video graphics circuitry, and audio processing circuitry. The internal peripheral devices include modems, network cards, etc. The motherboard includes a central processing unit (CPU), cache memory, a chip set, and may further include a portion of memory. Such a portion of memory may be read/write memory and/or ROM memory. The memory contained within the chassis is typically hard drive memory, floppy disk memory, CD memory and/or zip drive memory.
In operation, the central processing unit executes applications (e.g., word applications, drawing applications, etc.) and interfaces with the other devices of the computing system to provide the user with appropriate feedback regarding the execution of the application. As such the central processing unit communicates with the peripheral devices, the video graphics circuitry, and audio processing circuitry via the chip set. As is known, video graphics data received by the video graphics circuitry is processed and displayed on the monitor. In addition, audio data is processed by the audio processing circuit and provided to the speaker which renders the data audible. To facilitate the video graphics circuitry processing of data, an accelerated graphics port (AGP) bus has been provided to the memory via the chip set. By utilizing the AGP bus, the video graphics circuitry may store and retrieve data from the system memory without intervention from the central processing unit. Similarly, the PCI bus provides access to the system memory for the peripheral devices. Note that the audio processing circuitry may be coupled to the PCI bus to retrieve stored audio data such as synthesized audio data.
In the system of FIG. 4, the CPU and cache memory are typically fabricated on a single integrated circuit. The chip set is fabricated on two or more integrated circuits, while the video graphics circuitry is fabricated on a single integrated circuit and is typically mounted on a separate printed circuit (PC) board. Such an implementation is speed limited, bandwidth limited, and power dissipation limited (i.e., it consumes a substantial amount of power). For example, the transportation of data via the chip set does not run at the CPU rate. In a typical application, the data transference rate is 1/2n of the CPU rate. As such, the CPU often experiences delays when reading from and/or writing to main or system memory.
In addition, the data is transported via IC pins of the central processing unit, the chip set and the memory using TTL signaling technology. As is known, TTL signaling has a power dissipation that increases with the square of the frequency. Thus, a doubling of the frequency quadruples the power dissipation. Since most current CPUs are pushing the power dissipation envelope using a data transference frequency rate that is at most one-half of the CPU rate, increasing the data transference rate to the CPU rate would be impractical due to the quadrupling of the power dissipation.
The system of FIG. 4 is also bandwidth limited due to the impracticality of having a wider data bus. Current central processing units utilize a 64 bit bus. Accordingly, the CPU, the chip set and memory each require 64 pins to accommodate the bus. If a wider bus were desired, for example, 128 bits or 256 bits, each IC would require a corresponding number of pins, which currently is cost and area prohibitive. In addition, by increasing the number of signaling pins, the power dissipation increases accordingly. Thus, a doubling of pins doubles the power dissipation. As previously mentioned, since most current CPUs are pushing the power dissipation envelope, increasing the number of pins would be impractical.
Therefore, a need exists for a computer system that is not bandwidth limited, power dissipation limited or data transference rate limited as are current system architectures.